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 HD74HCT137
3-to-8-line Decoder/Demultiplexer with Address Latch
REJ03D0658-0200 (Previous ADE-205-546) Rev.2.00 Mar 30, 2006
Description
The HD74HCT137 implements a three-to-eight line decoder with latches on the three address inputs. When GL goes from low to high, the address present at the select inputs (A, B and C) is stored in the latches. As long as GL remains high no address changes will be recognized. Output enable controls, G1 and G2, control the state of the outputs independently of the select or latch-enable inputs. All of the outputs are high unless G1 is high and G2 is low. The HD74HCT137 is ideally suited for the implementation of glitch free decoders in stored-address applications in bus oriented systems.
Features
* * * * * * High Speed Operation: tpd (A, B, C to Y) = 16.5 ns typ (CL = 50 pF) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 V to 6 V Low Input Current: 1 A max Low Quiescent Supply Current: ICC (static) = 4 A max (Ta = 25C) Ordering Information
Part Name HD74HCT137FPEL HD74HCT137RPEL Package Type SOP-16 pin (JEITA) SOP-16 pin (JEDEC) Package Code (Previous Code) PRSP0016DH-B (FP-16DAV) FP Package Abbreviation Taping Abbreviation (Quantity) EL (2,000 pcs/reel) EL (2,500 pcs/reel)
PRSP0016DG-A RP (FP-16DNV) Note: Please consult the sales office for the above package availability.
Rev.2.00 Mar 30, 2006 page 1 of 7
HD74HCT137
Function Table
Inputs Enable G1 G2 C X H X L X X H L L H L L H L L H L L H L H H L H H L H H L H H L X High level Low level Irrelevant Select B X X L L H H L L H H X Outputs A X X L H L H L H L H X Y0 H H L H H H H H H H Y1 Y2 Y3 Y4 Y5 Y6 H H H H H H H H H H H H H H H H H H L H H H H H H L H H H H H H L H H H H H H L H H H H H H L H H H H H H L H H H H H H Output Corresponding to stored address L; all Others. H Y7 H H H H H H H H H L
GL X X L L L L L L L L H H: L: X:
Pin Arrangement
A1 B2 C3 GL 4 G2 5 G1 6 Y7 7 GND 8 B C GL G2 G1 Y7 Y6 A Y0 Y1 Y2 Y3 Y4 Y5 16 VCC 15 Y0 14 Y1 13 Y2 12 Y3 11 Y4 10 Y5 9 Y6
(Top view)
Rev.2.00 Mar 30, 2006 page 2 of 7
HD74HCT137
Logic Diagram
CK
A
CK CK CK
Y0
Y1 B Y2
C
Y3
CK
CK
Y4
GL
Y5
Y6
Y7 G2 G1
Absolute Maximum Ratings
Item Supply voltage range Input voltage Output voltage Output current DC current drain per VCC, GND DC input diode current DC output diode current Power dissipation per package Storage temperature Symbol VCC VIN VOUT IOUT ICC, IGND IIK IOK PT Tstg Rating -0.5 to +7.0 -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 25 50 20 20 500 -65 to +150 Unit V V V mA mA mA mA mW
C
Note: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of which may be realized at the same time.
Recommended Operating Conditions
Item Symbol Ratings Supply voltage VCC 4.5 to 5.5 Input / Output voltage VIN, VOUT 0 to VCC Operating temperature Ta -40 to 85 Input rise / fall time*1 tr, tf 0 to 500 Notes: 1. This item guarantees maximum limit when one input switches. Waveform: Refer to test circuit of switching characteristics. Unit V V Conditions
C
ns VCC = 4.5 V
Rev.2.00 Mar 30, 2006 page 3 of 7
HD74HCT137
Electrical Characteristics
Item Input voltage Output voltage Symbol VIH VIL VOH VOL Input current Quiescent supply current Iin ICC VCC (V) 4.5 to 5.5 4.5 to 5.5 4.5 4.5 4.5 4.5 5.5 5.5 Ta = 25C Min Typ Max 2.0 -- -- -- -- 0.8 4.4 -- -- 4.18 -- -- -- -- 0.1 -- -- 0.26 -- -- 0.1 -- -- 4.0 Ta = -40 to+85C Min Max 2.0 -- -- 0.8 4.4 -- 4.13 -- -- 0.1 -- 0.33 -- 1.0 -- 40 Unit V V V V A A Test Conditions
Vin = VIH or VIL IOH = -20 A IOH = -4 mA Vin = VIH or VIL IOL = 20 A IOL = 4 mA Vin = VCC or GND Vin = VCC or GND, Iout = 0 A
Switching Characteristics
(CL = 50 pF, Input tr = tf = 6 ns)
Item Propagation delay time Symbol VCC (V) tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Pulse width Setup time Hold time Output rise/fall time Input capacitance tw tsu th tTLH tTHL Cin 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 -- Ta = 25C Min -- -- -- -- -- -- -- -- 16 20 10 -- -- Typ 14 22 11 23 13 17 16 23 6 3 0 5 5 Max 34 48 26 39 30 39 35 50 -- -- -- 15 10 Ta = -40 to +85C Min -- -- -- -- -- -- -- -- 20 25 13 -- -- Max 43 60 33 49 38 49 44 63 -- -- -- 19 10 Unit ns ns ns ns ns ns ns ns pF Test Conditions A, B or C to Y G2 to Y G1 to Y GL to Y
Test Circuit
VCC VCC
Input Pulse Generator Zout = 50 Input Pulse Generator Zout = 50
See Function Table
A B C GL G2 G1 Y7 Y0
Output
CL = 50 pF Output
CL = 50 pF
Note : 1. CL includes probe and jig capacitance.
Rev.2.00 Mar 30, 2006 page 4 of 7
HD74HCT137 Waveforms
* Waveform - 1
6 ns 6 ns 90% 10% 90% 1.3 V 10%
Input A,B,C
90% 10%
90% 1.3 V 10%
VCC
1.3 V
tW tPLH Output Y
10% 90% 1.3 V
tW tPHL
90% 1.3 V 10%
0V
VOH VOL
tTLH
tTHL
Notes: 1. Input waveform: PRR 1 MHz, Zo = 50 , tr 6 ns, tf 6 ns 2. The output are measured one at a time with one transition per measurement.
* Waveform - 2
6 ns 6 ns 90% 1.3 V 10% 10%
G2
90% 1.3 V
VCC 0V
tPHL
90%
tPLH
1.3 V 10% 90% 1.3 V 10%
VOH VOL
Output Y
tTHL
tTLH
Notes: 1. Input waveform: PRR 1 MHz, Zo = 50 , tr 6 ns, tf 6 ns 2. The output are measured one at a time with one transition per measurement.
* Waveform - 3
6 ns 6 ns 90% 1.3 V 10%
G1
10%
90% 1.3 V
VCC 0V
tPHL
90%
tPLH
1.3 V 10% 90% 1.3 V 10%
VOH VOL
Output Y
tTHL
tTLH
Notes: 1. Input waveform: PRR 1 MHz, Zo = 50 , tr 6 ns, tf 6 ns 2. The output are measured one at a time with one transition per measurement.
Rev.2.00 Mar 30, 2006 page 5 of 7
HD74HCT137
* Waveform - 4
6 ns 90% 1.3 V 10% 10% 6 ns 90% 1.3 V
GL
VCC
1.3 V
tW tPLH Output Y
10% 90% 1.3 V
0V tPHL
90% 1.3 V 10%
VOH VOL
tTLH
tTHL
Notes: 1. Input waveform: PRR 1 MHz, Zo = 50 , tr 6 ns, tf 6 ns 2. The output are measured one at a time with one transition per measurement.
* Waveform - 5
tW Input A,B,C VCC
1.3 V 1.3 V
0V tsu th VCC GL
1.3 V
0V
Notes: 1. Input waveform: PRR 1 MHz, Zo = 50 , tr 6 ns, tf 6 ns 2. The output are measured one at a time with one transition per measurement.
Rev.2.00 Mar 30, 2006 page 6 of 7
HD74HCT137
Package Dimensions
JEITA Package Code P-SOP16-3.95x9.9-1.27 RENESAS Code PRSP0016DG-A Previous Code FP-16DNV MASS[Typ.] 0.15g
*1
D 9
F
16
NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
bp
E HE
Index mark
*2
Terminal cross section ( Ni/Pd/Au plating )
1 Z e
*3
c
8 bp x M L1
Reference Dimension in Millimeters Symbol
A1
L
y
Detail F
D E A2 A1 A bp b1 c c1 HE e x y Z L L1
Min Nom Max 9.90 10.30 3.95
0.10 0.14 0.25 1.75 0.34 0.40 0.46 0.15 0.20 0.25 0 8 5.80 6.10 6.20 1.27 0.25 0.15 0.635 0.40 0.60 1.27 1.08
JEITA Package Code P-SOP16-5.5x10.06-1.27
RENESAS Code PRSP0016DH-B
Previous Code FP-16DAV
MASS[Typ.] 0.24g
*1
D F 9
A
16
NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
bp
HE
E
Index mark
*2
Terminal cross section ( Ni/Pd/Au plating )
1 Z e
*3
8 bp x M L1
Reference Dimension in Millimeters Symbol
c
A1
y
L
Detail F
D E A2 A1 A bp b1 c c1 HE e x y Z L L1
Min Nom Max 10.06 10.5 5.50
0.00 0.10 0.20 2.20 0.34 0.40 0.46 0.15 0.20 0.25 0 8 7.50 7.80 8.00 1.27 0.12 0.15 0.80 0.50 0.70 0.90 1.15
Rev.2.00 Mar 30, 2006 page 7 of 7
A
Sales Strategic Planning Div.
Keep safety first in your circuit designs!
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1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.
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Colophon .6.0


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